CAD Engineer - Static Timing Analysis & Physical Design

As a member of our PD CAD team reporting to the STA manager, you will develop and support advanced Static Timing Analysis flows and methodologies while contributing to the broader Physical Design infrastructure. This role combines deep STA expertise with modern software engineering practices to deliver robust, scalable timing closure solutions for cutting-edge silicon designs. You will work closely with Physical Design teams, methodology teams, and EDA vendors to ensure timing signoff success across multiple advanced technology nodes.DescriptionYou will drive timing methodology development and support timing closure across multiple concurrent projects. Your work will span from flow automation and database-driven analysis to direct collaboration with design teams during critical tapeout phases.","responsibilities":"Develop and maintain automated STA flows, from constraint generation through signoff reportingBuild and optimize timing databases for cross-project analysis and historical trendingCreate Python-based tools for timing analysis, constraint validation, and ECO automationCollaborate with design teams to debug timing violations and develop closure strategiesInterface with EDA vendors on tool bring-up, validation, and advanced feature adoptionSupport multiple projects simultaneously during timing closure and tapeout phasesPreferred QualificationsBS/MS in Electrical Engineering, Computer Engineering, or Computer ScienceDemonstrated track record of successful timing closure on complex designsProficient in SQL with hands-on experience in MySQL and PostgreSQL for timing data management and analysisThis role offers the opportunity to shape next-generation timing methodologies while working with cutting-edge technologies and talented engineering teams across HWTech.Minimum QualificationsProven experience with PrimeTime for timing analysis, constraint development, and signoffDeep understanding of timing concepts: setup/hold analysis, clock domain crossing, multicycle paths, false paths, and timing exceptionsExperience with advanced timing concepts: OCV, statistical timing analysis, margins and variation analysisSolid understanding of RTL-to-GDSII flow with focus on timing-critical stagesKnowledge of power-aware timing analysis and low-power design methodologiesExpert-level Python programming for automation, data analysis, and tool integration","internalDetails":null,"eeoContent":null