Signal and Power Integrity Engineer

Job Description

About the Group

Ethernet SerDes IP (ESIP) group develops and delivers PLL's and all High Speed SerDes's to Intel devices.

Team delivers state of the art technologies as 112G, 224G and higher Ethernet SerDes.

Designs, develops, modifies and evaluates complex analog and mixed signal electronic parts, components or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems.

This is a dynamic team working with state of the art, unique technology.

If you are someone that loves a challenge, come join us and push the limits!

What You'll Be Doing

You will be responsible for signal/power integrity of IP covering silicon, package and board. As SIPD team member you will communicate across multiple disciplines / teams: Analog design and layout, Silicon integration, PCB & Package design/layout, mechanical design.

Provide implementation guidelines and feedback to silicon, package, board and system design groups.

Design and simulation of SerDes high-speed signals, co-simulate package, and PCB in HFSS

Perform feasibility study, design verification, and sign off along with lab correlations.

PDN analyses including model generation and time domain simulation.

Close work with Backend, package and board design teams for bumpout and ballout optimization

Chip-package-pcb co-design of 112 Gbps and above SerDes, following signal/power integrity considerations.

In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024 with ongoing support from Intel. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.

Qualifications

B.Sc./M.Sc./PhD in Electrical Engineering

5+ years of relevant experience

Good knowledge of 3D/2D EM simulation tools, electromagnetic and transmission line theory.

Experience in SI/PI methodology development, Full system signal integrity analysis, PDN modelling from die through package to PCB.

Advantage if you have an experience with HFSS, MATLAB, Python, SIwave, PowerSI and PowerDC, ADS, Redhawk, Totem, HSpice.
Fluent in English.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

JobType

Hybrid