Physical Verification Expert

Which department will you join?
Mobileye EyeC VLSI team - a group designing the chips for RADAR and LiDAR systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges

We’re looking for a Physical Verification Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading Physical Verification activities & methodologies for a brand new SoC, from definition to Tape Out.
Physical verification owner, defining Physical Verification methodologies & activities for Full Chip, Sub System & Block Level.
ESD planning & implementation; IO Pad, Bump, RDL planning.
Block Ownership from RTL to GDS.
Working with engineers to identify and overcome roadblocks and obstacles.
All you need is:
BSc/MSc in Electrical Engineering/Computer Science.
8 years of experience in VLSI backend (RTL2GDS).
5 years of experience in Full Chip Integration & verification on complex SoCs.
Physical Verification Expert (DRC/LVS/PERC).
Expert knowledge in floor planning, integration & signoff methodologies for hierarchical designs.
Experience with IO Pad, Bump & ESD planning.
Experience in technically leading complex backend activities, preferably of complete SoC's.
Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration & Physical Signoff).