ASIC Package Layout and NPI Engineer

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Haifa, Israel; Tel Aviv, Israel.
Minimum qualifications:
Bachelor's degree in Mechanical , Electrical Engineering, Material science, or equivalent practical experience.
5 years of experience in one of the following: Package/PCB layout design using Cadence/Mentor tools, semiconductor manufacturing processes, PCB manufacturing processes.
Experience in package/PCB designs for high-speed/power ICs such as CPUs, GPUs/ASIC/Chipset.

Preferred qualifications:
Experience with industry standards and regulatory requirements related to semiconductor manufacturing and packaging (e.g., JEDEC standards).
Experience with simulation and analysis tools (e.g., thermal, mechanical, signal integrity, power integrity analysis).
Experience in scripting and programming languages (e.g., Python, Perl, Tcl) for automation and data analysis.
Experience with Failure Analysis (FA) techniques and root cause investigations.
Knowledge of Design for Excellence (DFx) such as Design for Manufacturability, Testability principles.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a NPI and Layout package Engineer on the packaging team, you will be working on fast-paced products for consumer devices. In this role, you will work with Hardware Designers and Mechanical Engineers throughout the full product development life-cycle, supporting package outline, component placement and routing, using advanced package technologies while analyzing package reliability and manufacturability aspects.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Design the layout of package substrates using Cadence Allegro Package Designer.
Apply package substrate layout design rules from manufacturing point of view and electrical requirement considerations.
Generate high-quality design documents for substrate manufacturers and package assembly houses.
Enhance the package design work continuously by developing initiatives that drive efficiency and improve quality/cost/schedule of the package layout work.
Manage new ASIC packages during the NPI phase as the primary engineering owner, overseeing the product life-cycle from design lockdown to mass production release.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.