Senior Design Engineer

Tel AvivAbout The PositionWe are developing a next-generation compute-acceleration chip designed to power the future of LLM inference, the most compute-hungry and fastest-growing workload in AI.As the world pours trillions of dollars into scaling data-center AI, a massive bottleneck is emerging: delivering far more inference throughput at dramatically lower power. LLM inference now dominates the operational cost of AI, and accelerating it has become one of the most critical challenges in the entire industry.Our mission is to build a breakthrough architecture that leapfrogs today’s solutions from NVIDIA, AMD, Google TPU, and others — enabling unprecedented efficiency, throughput, and scalability.We operate in true startup mode: fast-paced, ambitious, and deeply technical. The project is challenging across architecture, RTL, verification, and schedule — and we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.Your Day to DayOwn the design, micro-architecture, and implementation of digital logic for a high-performance ASICTranslate system-level requirements into detailed micro-architecture and RTL designsDevelop high-quality RTL code in Verilog/SystemVerilogWork closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionalityParticipate in design reviews, propose improvements, and ensure compliance with coding and design guidelinesIntegrate and debug digital modules in simulation and lab environmentsSupport synthesis, timing closure, performance optimization, and power reduction activitiesCollaborate with verification teams to define test plans and ensure thorough coverageContribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the missionRequirementsRequiredAt least 5 years of experience in digital design for ASICBSc/MSc in Electrical Engineering, Computer Engineering, or related fieldStrong RTL development experience in Verilog/SystemVerilogSolid understanding of computer architecture, logic design, and digital system fundamentalsExperience with micro-architecture specification and documentationStrong communication skills and the ability to work cross-functionallySelf-driven, detail-oriented, capable of owning complex design challengesFluent in English, both verbal and writtenAdvantagesExperience with high-speed SERDES or parallel interfaces (PCIe, Aurora, Ethernet PHYs, custom links, etc.)Background in high-speed ASIC design, timing closure at high frequencies, and complex synchronization schemes across clock domainsFamiliarity with verification methodologies (UVM), simulation flows, and coverage-driven verificationExperience with scripting languages (Python, Perl, Tcl)Why should you be a TriEyoneer?Work on breakthrough AI acceleration technology that has the potential to reshape data-center computeJoin a fast-growing deep-tech environment backed by industry leadersBe part of a highly talented, multidisciplinary team solving cutting-edge engineering problemsModern offices in Tel Aviv with an excellent work environmentCompetitive benefits package: Free gym membership, parking, holidays and birthday gifts, Cibus, generous vacation allowance, happy hours, team events, etcGeneral statementTriEye is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.