Senior Design Engineer

Tel Aviv
About The Position

We are developing a next-generation compute-acceleration chip designed to power the future of LLM inference, the most compute-hungry and fastest-growing workload in AI.

As the world pours trillions of dollars into scaling data-center AI, a massive bottleneck is emerging: delivering far more inference throughput at dramatically lower power. LLM inference now dominates the operational cost of AI, and accelerating it has become one of the most critical challenges in the entire industry.

Our mission is to build a breakthrough architecture that leapfrogs today’s solutions from NVIDIA, AMD, Google TPU, and others — enabling unprecedented efficiency, throughput, and scalability.

We operate in true startup mode: fast-paced, ambitious, and deeply technical. The project is challenging across architecture, RTL, verification, and schedule — and we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.

The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.

Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission
Requirements

Required

At least 5 years of experience in digital design for ASIC
BSc/MSc in Electrical Engineering, Computer Engineering, or related field
Strong RTL development experience in Verilog/SystemVerilog
Solid understanding of computer architecture, logic design, and digital system fundamentals
Experience with micro-architecture specification and documentation
Strong communication skills and the ability to work cross-functionally
Self-driven, detail-oriented, capable of owning complex design challenges
Fluent in English, both verbal and written

Advantages

Experience with high-speed SERDES or parallel interfaces (PCIe, Aurora, Ethernet PHYs, custom links, etc.)
Background in high-speed ASIC design, timing closure at high frequencies, and complex synchronization schemes across clock domains
Familiarity with verification methodologies (UVM), simulation flows, and coverage-driven verification
Experience with scripting languages (Python, Perl, Tcl)
Why should you be a TriEyoneer?
Work on breakthrough AI acceleration technology that has the potential to reshape data-center compute
Join a fast-growing deep-tech environment backed by industry leaders
Be part of a highly talented, multidisciplinary team solving cutting-edge engineering problems
Modern offices in Tel Aviv with an excellent work environment
Competitive benefits package: Free gym membership, parking, holidays and birthday gifts, Cibus, generous vacation allowance, happy hours, team events, etc
General statement

TriEye is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.