Physical Design Engineer, Full Chip Layout

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

5 years of experience with physical design flows and methodologies (RTL2GDS).
Experience with semiconductor process technologies (deep submicron, advanced nodes like 5nm and below), and device physics (MOSFET/FINFET).
Experience with design for testability (DFT) and low-power design methodologies.
Experience with UPF (Unified Power Format) and its application in physical design.

Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

Experience with scripting languages such as Perl, Python, or Tcl.

Excellent analysis skills, with the ability to understand, debug, and resolve issues in the design flow.
About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team works on the world’s toughest problems, redefining what’s possible and the possible easy. We empower Google customers by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Googler Cloud customers, and billions of Google users worldwide. We’re at the center of amazing work at Google by being the “flywheel” that enables our advanced AI models, delivers computing power across global services, and offers platforms that developers use to build services.

In AI and Infrastructure, we shape the future of hyperscale computing by inventing and creating world-leading future technology, and drive global impact by contributing to Google infrastructure, from software to hardware (including building Vertex AI for Google Cloud). We work on complex technologies at a global scale with key players in the AI and systems space. Join a team of talented individuals who not only work together to keep data centers operating efficiently but also create a legacy of driving innovation by building some of the most complex systems technologies.

Responsibilities
Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement.
Design and implement efficient power delivery networks (power grids) to ensure stable power to all parts of the chip.
Develop and validate high-performance, low-power clock networks (Clock Tree Synthesis - CTS) to ensure proper synchronization across the entire chip.
Develop, enhance, and maintain custom scripts (e.g., Tcl, Perl, Python) for automation and improved efficiency.
Conduct extensive design rule checks (DRC) to ensure the layout adheres to manufacturing rules, performing layout versus schematic (LVS) checks to verify that the physical layout matches the logical design.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.