ASIC Design Engineer

Do you love crafting sophisticated solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices.

You will join an IP design team efforts to enable new use cases for our customers. You will collaborate with all fields, making a critical impact in getting functional products to millions of customers quickly!

Description
As an ASIC Design Engineer in the IP design team, you will work closely with architecture, design, and verification teams to build high-performance designs. Apply your knowledge of computer architecture and digital design to enable high-bandwidth processing pipelines!","responsibilities":"Coding high-quality RTL, with embedded assertions and cover points
Writing detailed micro-architectural specifications
Collaborating with multi-functional teams to explore solutions that improve performance while minimizing power and area
Working closely with design verification and formal verification teams to debug and verify functionality and performance

Preferred Qualifications
BS.c / MS.c in EE/ CE

Minimum Qualifications
5+ years of experience in digital design
Prefer previous experience in USB4, USB3, PCIe, and/or DisplayPort
Experience in SoC front-end ASIC RTL digital logic design using Verilog or System Verilog
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug
Good collaboration skills with strong written and verbal communication skills
Familiarity with low-power design techniques such as clock- and power-gating is a plus
Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks
Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with AI/ML applications, relevant scripting languages (Python, Perl, TCL)","internalDetails":null,"eeoContent":null