Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

BSc in Electrical engineering / Software engineering with distinction
Minimum of 5 years experience design/verification methodologies.
Experience with verification flows that include UVM.
Experience and knowledge of protocols like Ethernet, USB, SATA, PCIe (Not require all) – advantage.
Knowledge in RTL and TB Languages – Verilog or VHDL, SV or ‘e’ - Must
Knowledge in one or more of the following Languages: C / C++ / System-C / TLM for Design & Verification – advantage.
Team orientated, Good judgment under pressure
Fluent English
We’re doing work that matters. Help us solve what others can’t.