עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
35,000-50,000 ₪
We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.
It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.
It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA.
It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.
It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.
Key job responsibilities
- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).
- Verify IO sub-system features, including interconnect protocols and various accelerator engines.
- Develop and debug C embedded SW as part of hardware-software integration verification.
- Build and maintain UVM-based verification environments for various clusters and sub-systems.
- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.
- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).
- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.
- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.
- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.
It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.
It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA.
It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.
It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.
Key job responsibilities
- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).
- Verify IO sub-system features, including interconnect protocols and various accelerator engines.
- Develop and debug C embedded SW as part of hardware-software integration verification.
- Build and maintain UVM-based verification environments for various clusters and sub-systems.
- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.
- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).
- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.
- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.
- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.
Requirements:
Basic Qualifications
- 8+ years of experience in design verification of complex SoC or ASIC projects.
- Strong communication skills with the ability to collaborate across design, software, and physical design teams.
- Proven track record leading verification of IO sub-systems, interconnect fabrics, or system-level integration blocks.
- Deep expertise in UVM/SystemVerilog-based verification environments.
- Experience driving verification from product definition through post-tapeout silicon validation.
- Experience with performance verification methodologies alongside functional correctness.
Preferred Qualifications
- Strong knowledge of ARM interconnect protocols (AMBA CHI/ACE/AXI) and coherency verification.
- Experience with IO virtualization verification (SMMU, TLB, page table walks, memory attributes).
- C/C++ embedded software programming and firmware-level debug skills
- Experience with hardware-software co-verification.
- Familiarity with networking data paths and offload architectures.
- Understanding of physical design aspects and their impact on functional verification (e.g., clock domain crossings, power-aware verification).
Basic Qualifications
- 8+ years of experience in design verification of complex SoC or ASIC projects.
- Strong communication skills with the ability to collaborate across design, software, and physical design teams.
- Proven track record leading verification of IO sub-systems, interconnect fabrics, or system-level integration blocks.
- Deep expertise in UVM/SystemVerilog-based verification environments.
- Experience driving verification from product definition through post-tapeout silicon validation.
- Experience with performance verification methodologies alongside functional correctness.
Preferred Qualifications
- Strong knowledge of ARM interconnect protocols (AMBA CHI/ACE/AXI) and coherency verification.
- Experience with IO virtualization verification (SMMU, TLB, page table walks, memory attributes).
- C/C++ embedded software programming and firmware-level debug skills
- Experience with hardware-software co-verification.
- Familiarity with networking data paths and offload architectures.
- Understanding of physical design aspects and their impact on functional verification (e.g., clock domain crossings, power-aware verification).
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
חיפה
