עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
חינם. בלי פרסומות. בלי אותיות קטנות.
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כבר העליתם קו"ח בעבר? כניסה
מלאה
25,000-35,000 ₪
We are looking for a skilled Verification engineer to join a professional and dynamic team and take part in advanced, diverse technology projects in the fields of FPGA Verification, signal processing, controllers, and more. This role requires extensive experience in Verification, UVM methodology, SystemVerilog, FPGA / ASIC verification environments, RTL debugging, simulation tools, scripting, and working closely with FPGA development, system, architecture, and algorithm teams. A full-time on-site position based in Holon, Israel. Key Responsibilities:
* Develop verification environments using UVM methodology for FPGA verification across various projects.
* Work on verification projects involving signal processing, controllers, and additional advanced technologies.
* Define, architect, and develop verification environments from block-level to full-chip level.
* Work closely with FPGA development teams, system engineers, architecture teams, and algorithm engineers.
* Support RTL debugging from block level to system level.
* Develop verification environments using UVM methodology for FPGA verification across various projects.
* Work on verification projects involving signal processing, controllers, and additional advanced technologies.
* Define, architect, and develop verification environments from block-level to full-chip level.
* Work closely with FPGA development teams, system engineers, architecture teams, and algorithm engineers.
* Support RTL debugging from block level to system level.
Requirements:
Professional requirements: B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science - an advantage. 5+ years of experience in Verification, from TEST Plan definition through Coverage - mandatory. Hands-on experience with UVM methodology and SystemVerilog - mandatory. Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels - mandatory. Experience with RTL debugging from block level to system level - mandatory. Experience working with simulation tools; Questa Simulator is an advantage Experience writing scripts in Python, TCL, Bash / Csh - mandatory. Experience working in a Linux environment - mandatory. Experience working with FPGA, architecture, system, and algorithm teams. Very good technical English. Personality requirements: Strong analytical and problem-solving skills. Ability to work independently and as part of a team. Ability to work in a multidisciplinary environment.
Professional requirements: B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science - an advantage. 5+ years of experience in Verification, from TEST Plan definition through Coverage - mandatory. Hands-on experience with UVM methodology and SystemVerilog - mandatory. Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels - mandatory. Experience with RTL debugging from block level to system level - mandatory. Experience working with simulation tools; Questa Simulator is an advantage Experience writing scripts in Python, TCL, Bash / Csh - mandatory. Experience working in a Linux environment - mandatory. Experience working with FPGA, architecture, system, and algorithm teams. Very good technical English. Personality requirements: Strong analytical and problem-solving skills. Ability to work independently and as part of a team. Ability to work in a multidisciplinary environment.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
חינם. בלי פרסומות. בלי אותיות קטנות.
DOCX, DOC, PDF - בעברית או באנגלית
כבר העליתם קו"ח בעבר? כניסה
ערב
8 חודשים
