VLSI Backend Senior Engineer

Lead Full Chip Layout activities and methodologies for a new SoC, from definition to Tape Out. Perform Floor Planning from Top to Bottom and Bottom up at the Full Chip, Sub System, and Block levels. Collaborate closely with packaging, design, and architecture teams to develop the chip architecture. Explore various floorplan structures to achieve optimal area usage and ease of convergence. Manage sign-off timing convergence for high-performance designs at both the Full Chip and building block levels. Define the overall STA methodology, STA infrastructure, and sign-off convergence flows, working closely with block owners throughout the project. Collaborate with EDA (Electronic Design Automation) vendors on the development and qualification of the latest tool features.

Job Type: Full-time

Pay: 35,000.00₪ - 45,000.00₪ per month