עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
25,000-40,000 ₪
As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting-edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets.
Responsibilities
Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.
Develop and optimize the digital backend flow.
Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).
Collaborate with front-end designers to address timing and logical/physical interface issues.
Support tapeout preparation and final signoff processes.
Responsibilities
Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.
Develop and optimize the digital backend flow.
Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).
Collaborate with front-end designers to address timing and logical/physical interface issues.
Support tapeout preparation and final signoff processes.
Requirements:
Masters or PhD degree in Electrical/Electronic Engineering or a related field.
4+ years experience in digital IC backend implementation.
Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.
Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
Experience with advanced technology nodes (22nm or below preferred).
Skilled in Tcl scripting for automation of backend flows.
Experience in hierarchical or full-chip implementation is preferred.
Language: English at a proficient level. French is a plus.
Masters or PhD degree in Electrical/Electronic Engineering or a related field.
4+ years experience in digital IC backend implementation.
Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.
Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
Experience with advanced technology nodes (22nm or below preferred).
Skilled in Tcl scripting for automation of backend flows.
Experience in hierarchical or full-chip implementation is preferred.
Language: English at a proficient level. French is a plus.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
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