עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
חלקית
9,000-13,000 ₪
we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.
As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - its an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.
Key Responsibilities
Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent
As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - its an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.
Key Responsibilities
Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent
Requirements:
Pursuing a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related technical field
Ability to work at least 2 days a week at our Haifa/Tel Aviv center
Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
Fluent in Hebrew and English with the ability to work effectively in a team environment
Pursuing a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related technical field
Ability to work at least 2 days a week at our Haifa/Tel Aviv center
Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
Fluent in Hebrew and English with the ability to work effectively in a team environment
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
תל אביב - יפו
