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במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
35,000-55,000 ₪
Required SoC Security Architect, Cloud Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-Artificial Intelligence product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical. You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge.
As a Silicon Security Architect, you will be responsible for the "Security-First" mindset of our custom silicon. You will define the hardware security primitives that protect our infrastructure from the foundation up. You will bridge the gap between traditional architectural security (like access control and cryptography) and the physical reality of silicon (protecting against sophisticated lab-based attacks). You will define methods to protect sensitive information by silicon countermeasures. You will ensure that our accelerators are not only performant but also impenetrable to a wide range of adversaries.
Responsibilities
Define and document the security architecture and flows for systems on a chip (SoCs), covering hardware root of trust, secure boot, and cryptographic acceleration.
Lead the strategy and implementation of countermeasures against physical attacks, including side-channel analysis, fault injection, and silicon invasive attacks.
Conduct threat modeling and risk assessments for SoC subsystems, balancing security with power, performance, and area constraints.
Collaborate with hardware design and verification teams to ensure security features are implemented and resilient against both logical and physical vectors.
Drive the evaluation and selection of security intellectual property (IP), and provide technical leadership during multi-functional design reviews.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-Artificial Intelligence product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical. You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge.
As a Silicon Security Architect, you will be responsible for the "Security-First" mindset of our custom silicon. You will define the hardware security primitives that protect our infrastructure from the foundation up. You will bridge the gap between traditional architectural security (like access control and cryptography) and the physical reality of silicon (protecting against sophisticated lab-based attacks). You will define methods to protect sensitive information by silicon countermeasures. You will ensure that our accelerators are not only performant but also impenetrable to a wide range of adversaries.
Responsibilities
Define and document the security architecture and flows for systems on a chip (SoCs), covering hardware root of trust, secure boot, and cryptographic acceleration.
Lead the strategy and implementation of countermeasures against physical attacks, including side-channel analysis, fault injection, and silicon invasive attacks.
Conduct threat modeling and risk assessments for SoC subsystems, balancing security with power, performance, and area constraints.
Collaborate with hardware design and verification teams to ensure security features are implemented and resilient against both logical and physical vectors.
Drive the evaluation and selection of security intellectual property (IP), and provide technical leadership during multi-functional design reviews.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in SoC security architecture, hardware design, or security research.
Experience with hardware root of trust architecture, secure boot sequences, and hardware-based key management.
Experience designing or evaluating countermeasures against physical attacks (e.g., DPA or SPA, glitching, or EM attacks).
Experience with cryptographic algorithms and their hardware implementation trade-offs.
Preferred qualifications:
Masters or PhD in electrical engineering.
Experience with hardware safety mechanisms to meet safety goals (e.g., ASIL-B or ASIL-D and SIL 2 or SIL 3), including Logic-BIST (LBIST), software test libraries, and memory protection.
Experience with industry security standards (e.g., FIPS 140-3, Common Criteria).
Knowledge in functional safety primitives such as safety islands, distributed error monitors, and global error management flows.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in SoC security architecture, hardware design, or security research.
Experience with hardware root of trust architecture, secure boot sequences, and hardware-based key management.
Experience designing or evaluating countermeasures against physical attacks (e.g., DPA or SPA, glitching, or EM attacks).
Experience with cryptographic algorithms and their hardware implementation trade-offs.
Preferred qualifications:
Masters or PhD in electrical engineering.
Experience with hardware safety mechanisms to meet safety goals (e.g., ASIL-B or ASIL-D and SIL 2 or SIL 3), including Logic-BIST (LBIST), software test libraries, and memory protection.
Experience with industry security standards (e.g., FIPS 140-3, Common Criteria).
Knowledge in functional safety primitives such as safety islands, distributed error monitors, and global error management flows.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
תל אביב - יפו
