עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
30,000-45,000 ₪
As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.
Key Responsibilities
Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle
Key Responsibilities
Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle
Requirements:
B.Sc. in Electrical Engineering, Computer Engineering, or a related field
10+ years of proven hands-on experience in ASIC verification, with at least 2+ years in a technical leadership or people management role
Deep hands-on expertise in architecting complex small-to-medium (IPs, blocks, sub-systems) verification environments from scratch
Expert-level knowledge of verification methodologies, specifically UVM
Proven ability to manage project timelines, resource allocation, and the professional growth of IP verification team members
Exceptional interpersonal skills with the ability to navigate a fast-paced, collaborative R&D environment and influence stakeholders
B.Sc. in Electrical Engineering, Computer Engineering, or a related field
10+ years of proven hands-on experience in ASIC verification, with at least 2+ years in a technical leadership or people management role
Deep hands-on expertise in architecting complex small-to-medium (IPs, blocks, sub-systems) verification environments from scratch
Expert-level knowledge of verification methodologies, specifically UVM
Proven ability to manage project timelines, resource allocation, and the professional growth of IP verification team members
Exceptional interpersonal skills with the ability to navigate a fast-paced, collaborative R&D environment and influence stakeholders
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
חיפה
