עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
25,000-35,000 ₪
Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.
Key Responsibilities:
* Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
* Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
* CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
* Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
* Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.
Key Responsibilities:
* Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
* Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
* CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
* Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
* Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.
Requirements:
Minimum Qualifications:
5+ years of professional functional verification experience for FPGA or ASIC designs.
Proven, hands-on mastery of UVM and building complete verification environments.
Strong command of SystemVerilog and Verilog.
Extensive experience with EDA tools (specifically Questa) and complex hardware debugging.
Preferred Qualifications:
Proficiency in Matlab for DPI or bit-exact modeling.
Scripting experience (Python/Tcl/Bash) for building automated CI/CD regression flows.
Minimum Qualifications:
5+ years of professional functional verification experience for FPGA or ASIC designs.
Proven, hands-on mastery of UVM and building complete verification environments.
Strong command of SystemVerilog and Verilog.
Extensive experience with EDA tools (specifically Questa) and complex hardware debugging.
Preferred Qualifications:
Proficiency in Matlab for DPI or bit-exact modeling.
Scripting experience (Python/Tcl/Bash) for building automated CI/CD regression flows.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
רעננה
