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במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
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כבר העליתם קו"ח בעבר? כניסה
מלאה
22,000-32,000 ₪
you will be developing physical design, sta, logic eq, power integrity flows and methodologies for implementation of networking chips and socs.
work closely with block owners, full chip sta engineers to assure high quality and timely convergence.
come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, ir-drop, em and back-end verification across multiple projects.
work closely with block owners, full chip sta engineers to assure high quality and timely convergence.
come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, ir-drop, em and back-end verification across multiple projects.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering (or equivalent experience).
2+ years of fulltime relevant experience in the areas listed below.
proven experience and strong knowledge in key technical domains, including: physical design, backend cad (computer-aided design), sta (static timing analysis) and timing closure methodologies.
familiarity with industry-standard tools like primetime (sta) and primepower (power estimation).
self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams
ways to stand out from the crowd:
experience in signoff domains: sta (primetime), power estimation (primepower), power integrity (redhawk), formal eq. (formality)
knowledge in tcl/ PERL / Python
versatile
great teammate
what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering (or equivalent experience).
2+ years of fulltime relevant experience in the areas listed below.
proven experience and strong knowledge in key technical domains, including: physical design, backend cad (computer-aided design), sta (static timing analysis) and timing closure methodologies.
familiarity with industry-standard tools like primetime (sta) and primepower (power estimation).
self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams
ways to stand out from the crowd:
experience in signoff domains: sta (primetime), power estimation (primepower), power integrity (redhawk), formal eq. (formality)
knowledge in tcl/ PERL / Python
versatile
great teammate
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
חינם. בלי פרסומות. בלי אותיות קטנות.
DOCX, DOC, PDF - בעברית או באנגלית
כבר העליתם קו"ח בעבר? כניסה
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