עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
35,000-55,000 ₪
We are looking for a visionary Senior System Architect to lead the charge in defining how we move data at speeds the world has never seen. We want to bridge the gap between silicon and the rack, ensuring our NVLink and InfiniBand fabrics remain the gold standard for performance. This is a chance to join a team where we don't just follow industry standards-we set them!
You will work at the intersection of Signal Integrity (SI), Mechanical Engineering, and System Protocol design to ensure that our NVLink and InfiniBand/Ethernet fabrics scale to terabit-per-second speeds with industry-leading power efficiency and reliability.
What Youll Be Doing:
Architectural Definition: Lead the end-to-end definition of high-speed interconnect systems for next-gen AI platforms (e.g., Rubin and beyond), focusing on 224G/448G PAM4 lanes and beyond.
Technology Roadmap: Evaluate and select pioneering technologies such as Co-Packaged Optics (CPO), Silicon Photonics, and advanced OSFP/QSFP-DD form factors.
System Co-Design: Collaborate with ASIC, Thermal, and PCB teams to optimize the "Silicon-to-Connector" path, minimizing insertion loss and improving signal integrity.
Standardization Leadership: Represent us in industry standards bodies (e.g., IEEE 802.3, OCP, MSA) to influence the future of high-speed connector and cable specifications.
Vendor Ecosystem: Work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet our unique performance requirements.
Performance Modeling: Conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (Copper vs. Optical).
You will work at the intersection of Signal Integrity (SI), Mechanical Engineering, and System Protocol design to ensure that our NVLink and InfiniBand/Ethernet fabrics scale to terabit-per-second speeds with industry-leading power efficiency and reliability.
What Youll Be Doing:
Architectural Definition: Lead the end-to-end definition of high-speed interconnect systems for next-gen AI platforms (e.g., Rubin and beyond), focusing on 224G/448G PAM4 lanes and beyond.
Technology Roadmap: Evaluate and select pioneering technologies such as Co-Packaged Optics (CPO), Silicon Photonics, and advanced OSFP/QSFP-DD form factors.
System Co-Design: Collaborate with ASIC, Thermal, and PCB teams to optimize the "Silicon-to-Connector" path, minimizing insertion loss and improving signal integrity.
Standardization Leadership: Represent us in industry standards bodies (e.g., IEEE 802.3, OCP, MSA) to influence the future of high-speed connector and cable specifications.
Vendor Ecosystem: Work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet our unique performance requirements.
Performance Modeling: Conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (Copper vs. Optical).
Requirements:
Deep understanding of Channel Operating Margin (COM), BER, FEC, and crosstalk in 112G and 224G PAM4 environments.
Expert knowledge of PCIe (Gen 6/7), Ethernet (800G/1.6T).
Sophisticated knowledge of OSFP, QSFP-DD, and SFP-DD form factors; experience with DAC, ACC, and AOC architectures.
Familiarity with Silicon Photonics, CPO, and MPO/APC fiber architectures.
B.Sc./M.Sc. or PhD or equivalent experience in Electrical Engineering, Physics, or related field.
12+ years in high-speed hardware design or system architecture, with a proven track record of shipping high-volume data center products.
Ability to predict technology bottlenecks 3-5 years in advance.
Multi-functional Influence: Ability to align Software, Hardware, and Thermal teams on a single architectural vision.
Exceptional ability to present complex trade-offs to executive leadership.
Deep understanding of Channel Operating Margin (COM), BER, FEC, and crosstalk in 112G and 224G PAM4 environments.
Expert knowledge of PCIe (Gen 6/7), Ethernet (800G/1.6T).
Sophisticated knowledge of OSFP, QSFP-DD, and SFP-DD form factors; experience with DAC, ACC, and AOC architectures.
Familiarity with Silicon Photonics, CPO, and MPO/APC fiber architectures.
B.Sc./M.Sc. or PhD or equivalent experience in Electrical Engineering, Physics, or related field.
12+ years in high-speed hardware design or system architecture, with a proven track record of shipping high-volume data center products.
Ability to predict technology bottlenecks 3-5 years in advance.
Multi-functional Influence: Ability to align Software, Hardware, and Thermal teams on a single architectural vision.
Exceptional ability to present complex trade-offs to executive leadership.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
חדרה
