עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
25,000-35,000 ₪
We operate in true startup mode: fast-paced, ambitious, and deeply technical. The project is challenging across architecture, RTL, verification, and schedule and we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.
The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.
Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission
The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.
Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission
Requirements:
Required:
At least 5 years of experience in digital design for ASIC.
BSc/MSc in Electrical Engineering, Computer Engineering, or related field
Strong RTL development experience in Verilog/SystemVerilog.
Solid understanding of computer architecture, logic design, and digital system fundamentals.
Experience with micro-architecture specification and documentation.
Strong communication skills and the ability to work cross-functionally.
Self-driven, detail-oriented, capable of owning complex design challenges
Fluent in English, both verbal and written.
Advantages:
Experience with high-speed SERDES or parallel interfaces (PCIe, Aurora, Ethernet PHYs, custom links, etc.).
Background in high-speed ASIC design, timing closure at high frequencies, and complex synchronization schemes across clock domains.
Familiarity with verification methodologies (UVM), simulation flows, and coverage-driven verification.
Experience with scripting languages (Python, Perl, Tcl).
Required:
At least 5 years of experience in digital design for ASIC.
BSc/MSc in Electrical Engineering, Computer Engineering, or related field
Strong RTL development experience in Verilog/SystemVerilog.
Solid understanding of computer architecture, logic design, and digital system fundamentals.
Experience with micro-architecture specification and documentation.
Strong communication skills and the ability to work cross-functionally.
Self-driven, detail-oriented, capable of owning complex design challenges
Fluent in English, both verbal and written.
Advantages:
Experience with high-speed SERDES or parallel interfaces (PCIe, Aurora, Ethernet PHYs, custom links, etc.).
Background in high-speed ASIC design, timing closure at high frequencies, and complex synchronization schemes across clock domains.
Familiarity with verification methodologies (UVM), simulation flows, and coverage-driven verification.
Experience with scripting languages (Python, Perl, Tcl).
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
תל אביב - יפו
ערב
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