עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
25,000-35,000 ₪
we are looking for a Senior Logic Design Engineer to join the ride as we spearhead the next revolution in electronics and lead the IP Integration Enablement.
Responsibilities
Customer-Centric Integration Leadership
Act as the voice of the customer in internal R&D reviews, advocating for integration simplicity, design compatibility, and customer usability.
Identify and address integration challenges early in the development cycle to ensure seamless adoption by customer design teams.
Integration Infrastructure & Collateral
Define and oversee all integration-related deliverables, ensuring quality, consistency, and alignment with customer integration needs.
Review and contribute to the development of collateral, including:
o Lint, CDC, RDC and IPXACT views
o Register maps, ICL and PDL files
o Simulation and emulation views
o Integration testbenches and verification collaterals
Out-of-the-Box Integration Benchmark & Regression
Develop and maintain an out-of-the-box environment to evaluate IP integration from the customers perspective.
Validate end-to-end IP Integration in representative SoC contexts using the Proteus IP integration flow as described in the integration guide.
Develop and maintain integration regression tests to ensure integration KPIs are consistently met.
Cross-Functional Collaboration
Train and mentor Application Engineers on the Proteus IP integration playbook, ensuring consistent and effective deployment across customer projects.
Provide expert support for complex integration challenges escalated through the field teams.
Gather structured feedback from Application Engineers and customers to continuously refine integration methodologies and improve the overall integration experience.
Responsibilities
Customer-Centric Integration Leadership
Act as the voice of the customer in internal R&D reviews, advocating for integration simplicity, design compatibility, and customer usability.
Identify and address integration challenges early in the development cycle to ensure seamless adoption by customer design teams.
Integration Infrastructure & Collateral
Define and oversee all integration-related deliverables, ensuring quality, consistency, and alignment with customer integration needs.
Review and contribute to the development of collateral, including:
o Lint, CDC, RDC and IPXACT views
o Register maps, ICL and PDL files
o Simulation and emulation views
o Integration testbenches and verification collaterals
Out-of-the-Box Integration Benchmark & Regression
Develop and maintain an out-of-the-box environment to evaluate IP integration from the customers perspective.
Validate end-to-end IP Integration in representative SoC contexts using the Proteus IP integration flow as described in the integration guide.
Develop and maintain integration regression tests to ensure integration KPIs are consistently met.
Cross-Functional Collaboration
Train and mentor Application Engineers on the Proteus IP integration playbook, ensuring consistent and effective deployment across customer projects.
Provide expert support for complex integration challenges escalated through the field teams.
Gather structured feedback from Application Engineers and customers to continuously refine integration methodologies and improve the overall integration experience.
Requirements:
B.Sc. or M.Sc. in Electrical or Computer Engineering.
7+ years of experience in ASIC/SoC design or integration, with proven ownership of IP-level or subsystem integration.
Strong background in RTL design, handoff methodologies and signoff tools (Lint, CDC, etc.).
Proficiency in scripting (Python or equivalent) for flow automation.
Experience with System-Verilog and simulation environments for integration validation.
Strong interpersonal and communication skills, with the ability to represent R&D in customer-facing contexts.
B.Sc. or M.Sc. in Electrical or Computer Engineering.
7+ years of experience in ASIC/SoC design or integration, with proven ownership of IP-level or subsystem integration.
Strong background in RTL design, handoff methodologies and signoff tools (Lint, CDC, etc.).
Proficiency in scripting (Python or equivalent) for flow automation.
Experience with System-Verilog and simulation environments for integration validation.
Strong interpersonal and communication skills, with the ability to represent R&D in customer-facing contexts.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
