עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
חינם. בלי פרסומות. בלי אותיות קטנות.
DOCX, DOC, PDF - בעברית או באנגלית
כבר העליתם קו"ח בעבר? כניסה
מלאה
30,000-45,000 ₪
Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.
Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years of experience in IP or Full Chip or IP level STA on complex SoCs.
Expert knowledge in timing closure & signoff methodologies.
Experience with DFT architecture, Async timing concepts & verification.
Experience in technically leading complex backend activities, preferably of complete SoC's.
Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, FP, PnR, CTS, STA, LP, EM/IR, Chip Integration).
Team player with excellent communication skills, customer orientation, and a can-do attitude.
BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years of experience in IP or Full Chip or IP level STA on complex SoCs.
Expert knowledge in timing closure & signoff methodologies.
Experience with DFT architecture, Async timing concepts & verification.
Experience in technically leading complex backend activities, preferably of complete SoC's.
Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, FP, PnR, CTS, STA, LP, EM/IR, Chip Integration).
Team player with excellent communication skills, customer orientation, and a can-do attitude.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
חינם. בלי פרסומות. בלי אותיות קטנות.
DOCX, DOC, PDF - בעברית או באנגלית
כבר העליתם קו"ח בעבר? כניסה
משרות נוספות מומלצות עבורך
-
Application Engineer - Physical Design (Back-End)
-
פתח תקווה
Cadence
-
-
Physical Designer Engineer, Cloud
-
חיפה
גוגל ישראל
-
-
Full Chip CAD Physical Design Engineer
-
חיפה
גוגל ישראל
-
-
Senior Silicon Physical Design Engineer
-
חיפה
גוגל ישראל
-
-
Physical Verification Engineer
-
תל אביב - יפו
NVIDIA
-
-
Senior Physical Verification Engineer
-
תל אביב - יפו
NVIDIA
-
