עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
30,000-45,000 ₪
Senior frontend TFM Engineer (5850) Join us in shaping the future of AI connectivity!
This is a unique opportunity to help build a new Israeli R&D site from the ground up. Were looking for highly experienced and visionary engineers to define the technological foundation of our next-generation AI infrastructure.
As a Senior frontend TFM (Tools, Flows, and Methodology) Engineer, youll be part of our silicon design team driving the development of robust, scalable, and automated design environments for cutting-edge ASIC and SOC programs.
Why us
Were redefining AI infrastructure from the ground up.
Join a world-class multidisciplinary team and take a key role in shaping the design environment and methodologies behind the industrys most advanced AI connectivity silicon. Key Responsibilities:
Define, develop, and maintain EDA flows for synthesis, lint, CDC, equivalence check, and STA.
Integrate frontend design environments across RTL design, verification, and physical design teams.
Evaluate and deploy new EDA tools and methodologies to improve design productivity and quality.
Develop automation scripts ( Python, Tcl, Make, etc.) for continuous integration and regression flows.
Collaborate with design and Verification engineers to ensure smooth handoffs and consistent flows.
Own methodology documentation and define best practices for frontend design enablement.
This is a unique opportunity to help build a new Israeli R&D site from the ground up. Were looking for highly experienced and visionary engineers to define the technological foundation of our next-generation AI infrastructure.
As a Senior frontend TFM (Tools, Flows, and Methodology) Engineer, youll be part of our silicon design team driving the development of robust, scalable, and automated design environments for cutting-edge ASIC and SOC programs.
Why us
Were redefining AI infrastructure from the ground up.
Join a world-class multidisciplinary team and take a key role in shaping the design environment and methodologies behind the industrys most advanced AI connectivity silicon. Key Responsibilities:
Define, develop, and maintain EDA flows for synthesis, lint, CDC, equivalence check, and STA.
Integrate frontend design environments across RTL design, verification, and physical design teams.
Evaluate and deploy new EDA tools and methodologies to improve design productivity and quality.
Develop automation scripts ( Python, Tcl, Make, etc.) for continuous integration and regression flows.
Collaborate with design and Verification engineers to ensure smooth handoffs and consistent flows.
Own methodology documentation and define best practices for frontend design enablement.
Requirements:
Requirements:
B.Sc. / M.Sc. in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in frontend design TFM, CAD, or design infrastructure roles.
Strong understanding of RTL design and synthesis flows (Verilog / SystemVerilog).
Hands-on experience with Synopsys, Cadence, or Siemens EDA tools.
Proficient in scripting languages ( Python, PERL, Tcl).
Familiarity with version control systems (Git, Perforce) and CI/CD flows.
Excellent analytical, problem-solving, and collaboration skills. Nice to Have:
Experience with AI, networking, or high-performance ASICs.
Exposure to open-source EDA tools or custom automation frameworks.
Knowledge of DFT, backend, or PnR flows.
Requirements:
B.Sc. / M.Sc. in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in frontend design TFM, CAD, or design infrastructure roles.
Strong understanding of RTL design and synthesis flows (Verilog / SystemVerilog).
Hands-on experience with Synopsys, Cadence, or Siemens EDA tools.
Proficient in scripting languages ( Python, PERL, Tcl).
Familiarity with version control systems (Git, Perforce) and CI/CD flows.
Excellent analytical, problem-solving, and collaboration skills. Nice to Have:
Experience with AI, networking, or high-performance ASICs.
Exposure to open-source EDA tools or custom automation frameworks.
Knowledge of DFT, backend, or PnR flows.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
