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במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
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כבר העליתם קו"ח בעבר? כניסה
מלאה
22,000-32,000 ₪
Our EYEQ VLSI team is looking for an ASIC design engineer to be involved in the development of our current and future SoC. Working on the cutting-edge technologies to deliver our EyeQ SoC family for ADAS and autonomous vehicles.
What will your job look like:
You will work on developing the next generation of our SoC for ADAS and AV.
Be involved in deep understanding of the design at multiple levels: the micro-architecture, features and specification.
Design and implement new proprietary IPs and system features.
Integrate third parties and proprietary IPs in a multi-clock domain system on chip.
Verification, synthesis, static timing analysis, and closure.
Power and Area Optimizations.
You will become familiar with design environment, flow, tools, methodologies and optimization methods
Collaborate with cross-functional teams, including Product Definition, Verification, Software, and Physical design.
What will your job look like:
You will work on developing the next generation of our SoC for ADAS and AV.
Be involved in deep understanding of the design at multiple levels: the micro-architecture, features and specification.
Design and implement new proprietary IPs and system features.
Integrate third parties and proprietary IPs in a multi-clock domain system on chip.
Verification, synthesis, static timing analysis, and closure.
Power and Area Optimizations.
You will become familiar with design environment, flow, tools, methodologies and optimization methods
Collaborate with cross-functional teams, including Product Definition, Verification, Software, and Physical design.
Requirements:
B.Sc. in Electrical Engineering/Computer Engineering.
3 years of experience as an ASIC/FPGA designer.
Familiar with simulation tools/environments, verification methodologies.
Experience with a full design cycle RTL/Verification/Synthesis and timing closure/CDC/ Lint.
Strong team player, solid interpersonal skills.
Entrepreneurial can-do attitude, self-motivated, able to work independently.
Scripting experience using several of the following: Python, Perl, TCL Advantage.
B.Sc. in Electrical Engineering/Computer Engineering.
3 years of experience as an ASIC/FPGA designer.
Familiar with simulation tools/environments, verification methodologies.
Experience with a full design cycle RTL/Verification/Synthesis and timing closure/CDC/ Lint.
Strong team player, solid interpersonal skills.
Entrepreneurial can-do attitude, self-motivated, able to work independently.
Scripting experience using several of the following: Python, Perl, TCL Advantage.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 90,000 משרות • אלפי משרות חדשות בכל יום
חינם. בלי פרסומות. בלי אותיות קטנות.
DOCX, DOC, PDF - בעברית או באנגלית
כבר העליתם קו"ח בעבר? כניסה
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