עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
28,000-40,000 ₪
We are looking to hire a Chip Design Verification Engineer to join our Chip Design group. The work environment is versatile, educational, dynamic and challenging as our employees are currently working on innovative, next-generation networking devices at the forefront of technology in terms of performance and power efficiency. Daily work involves all aspects of chip development: Design, Micro- Architecture, Firmware, and Verification. Work with the best and become one of the best!
What you will be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
What you will be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
Requirements:
B.SC./ M.SC. in Computer Engineering /Electrical Engineering/Communication Engineering or equivalent experience.
3+ years of proven experience in RTL FrontEnd Asic Verification (Chip Design).
Deep and vast experience with System-Verilog UVM.
Ability to technically lead the verification of an IP block.
Familiarity with the different verification tools and methodologies.
Deep knowledge in HDL (Verilog/VHDL).
High Level English
B.SC./ M.SC. in Computer Engineering /Electrical Engineering/Communication Engineering or equivalent experience.
3+ years of proven experience in RTL FrontEnd Asic Verification (Chip Design).
Deep and vast experience with System-Verilog UVM.
Ability to technically lead the verification of an IP block.
Familiarity with the different verification tools and methodologies.
Deep knowledge in HDL (Verilog/VHDL).
High Level English
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
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