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במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
45,000-70,000 ₪
Required Expert & Team leader in high-performance computing network architecture
Hod Hasharon \ Haifa
Job Description:
A research unit within Huawei that build a solid foundation and leading competitiveness of network technologies, supporting the business success of all BUs. NTLab leads next-generation network technology innovation, opening up new industry space, Focus on Computing/Cloud/Storage network and Net 6G core innovation, build a leading computing network in AI era, improve industry competitiveness; Continuously research on Ethernet technology system, expand new scenarios and spaces; Root in basic network technologies, build public network platforms
The High-performance Computing Network Architecture Team within NTLab is responsible for next generation computing network architecture research, ranging from network architecture evolution technology to large scale network technology (e.g. Ethernet/IB/RoCE), bus network technology (PCIE/CXL), chiplet interconnect technology and strategic technology planning.
Responsibilities:
Drive architectural definition, technology insight, and product planning for next-generation chiplet-based switching systems, switching ASIC, data processing unit and etc
Design scalable, high-throughput, and low-latency interconnect architectures leveraging Network-on-Chip (NoC) principles and chiplet technologies
Lead system-level architecture and chip definition activities for large-scale switching ASICs used in modern data center or cloud infrastructure
Analyze system performance, traffic flow, and interconnect bottlenecks in multi-chiplet switching designs
Evaluate and propose novel solutions to optimize data movement and bandwidth utilization across chiplet-based systems
Collaborate closely with packaging, physical design, and signal integrity teams to define inter-die connectivity standards and partitioning strategies
Engage with external research institutes, academic partners, and vendors to track emerging trends in chiplet packaging, die-to-die protocols, and NoC frameworks
Drive proof-of-concept implementations and participate in innovation and patenting processes
Mentor and coach less experienced staff members
Generate novel ideas and protect them with IPR fillings.
Hod Hasharon \ Haifa
Job Description:
A research unit within Huawei that build a solid foundation and leading competitiveness of network technologies, supporting the business success of all BUs. NTLab leads next-generation network technology innovation, opening up new industry space, Focus on Computing/Cloud/Storage network and Net 6G core innovation, build a leading computing network in AI era, improve industry competitiveness; Continuously research on Ethernet technology system, expand new scenarios and spaces; Root in basic network technologies, build public network platforms
The High-performance Computing Network Architecture Team within NTLab is responsible for next generation computing network architecture research, ranging from network architecture evolution technology to large scale network technology (e.g. Ethernet/IB/RoCE), bus network technology (PCIE/CXL), chiplet interconnect technology and strategic technology planning.
Responsibilities:
Drive architectural definition, technology insight, and product planning for next-generation chiplet-based switching systems, switching ASIC, data processing unit and etc
Design scalable, high-throughput, and low-latency interconnect architectures leveraging Network-on-Chip (NoC) principles and chiplet technologies
Lead system-level architecture and chip definition activities for large-scale switching ASICs used in modern data center or cloud infrastructure
Analyze system performance, traffic flow, and interconnect bottlenecks in multi-chiplet switching designs
Evaluate and propose novel solutions to optimize data movement and bandwidth utilization across chiplet-based systems
Collaborate closely with packaging, physical design, and signal integrity teams to define inter-die connectivity standards and partitioning strategies
Engage with external research institutes, academic partners, and vendors to track emerging trends in chiplet packaging, die-to-die protocols, and NoC frameworks
Drive proof-of-concept implementations and participate in innovation and patenting processes
Mentor and coach less experienced staff members
Generate novel ideas and protect them with IPR fillings.
Requirements:
B.Sc or higher in Electrical Engineering, Computer Engineering, or related discipline. M.Sc or PhD Advantage
Solid experience in the switching industry with a strong focus on ASIC design, architecture, or product definition
Hands-on experience in chiplet systems, die-to-die interconnects, or NoC topologies (e.g., mesh, torus, ring, hierarchical)
Expertise in ASIC microarchitecture and system-level partitioning
Strong system thinking and ability to define, simulate, and validate architectural decisions
Familiarity with packaging constraints, chiplet interface protocols (e.g., UCIe, BoW), and interposer technologies Advantage
Experience working across multi-disciplinary teams including physical design, packaging, verification, and firmware Advantage
Knowledge of RDMA, RoCE, or network adapters Advantage
Good theoretical understanding in at least one of the following: computer architecture, distributed system and application algorithms, memory systems and network protocols as well as operating system kernels, micro-architecture of ASIC chips, large scale network and computing bus network stacks
Track record in innovation, patents, or technical publications Advantage
Skills:
Willingness to travel occasionally for technical workshops, conferences, or project reviews
Strong communication skills and fluency in English.
B.Sc or higher in Electrical Engineering, Computer Engineering, or related discipline. M.Sc or PhD Advantage
Solid experience in the switching industry with a strong focus on ASIC design, architecture, or product definition
Hands-on experience in chiplet systems, die-to-die interconnects, or NoC topologies (e.g., mesh, torus, ring, hierarchical)
Expertise in ASIC microarchitecture and system-level partitioning
Strong system thinking and ability to define, simulate, and validate architectural decisions
Familiarity with packaging constraints, chiplet interface protocols (e.g., UCIe, BoW), and interposer technologies Advantage
Experience working across multi-disciplinary teams including physical design, packaging, verification, and firmware Advantage
Knowledge of RDMA, RoCE, or network adapters Advantage
Good theoretical understanding in at least one of the following: computer architecture, distributed system and application algorithms, memory systems and network protocols as well as operating system kernels, micro-architecture of ASIC chips, large scale network and computing bus network stacks
Track record in innovation, patents, or technical publications Advantage
Skills:
Willingness to travel occasionally for technical workshops, conferences, or project reviews
Strong communication skills and fluency in English.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
רמת גן
ערב
12 חודשים
