עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!

במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.

מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.

חברה בתחום תקשורת וסלולר

הרצליה

חברה בתחום תקשורת וסלולר

הרצליה
מלאה
30,000-45,000 ₪ הערכה מבוססת AI ולא שכר שהתקבל מהמעסיק
הערכה מבוססת AI ולא שכר של המעסיק

Lead the complete DFT solutions in a chip design by working with chip DFT team to document DFT specifications, and define the SoC test interface Develop and implement DFT architecture Work with the validation team to verify DFT implementations and implement design changes Generate structural test vectors, analyze and improve coverage Work with designers on STA, physical, power and logical issues Work with Test Engineers to bring up test vectors on silicon.

Requirements:
Minimum Qualifications:
5+ years of DFT experience, leading DFT efforts for complex chip designs.
We are counting on your expertise and knowledge about industrial standards and practices in DFT - including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
You have experience developing DFT specifications and driving DFT architecture and methods for designs.
You are confident with Verilog and / or VHDL, and have experience with simulators and waveform debugging tools.
By now you are demonstrating proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon.
You can debug ATPG patterns, compressed ATPG patterns, MBIST, and JTAG/1500 related issues.
You have experienced with STA constraints development and analysis for DFT modes and SDF simulations.
You love conducting experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data.

Preferred Qualifications:
BS.c/ MS.c in EE/ CE.

This position is open to all candidates.