עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
30,000-50,000 ₪
Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
2 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in Design for Testing (DFT) scan design and verification.
Experience with Design for Testing (DFT) techniques and tools, Application-Specific Integrated Circuit (ASIC) Design for Testing synthesis, simulation, and verification flow.
Preferred qualifications:
Master's degree in Electrical Engineering.
Experience working with Automated Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
Experience in System on a chip (SoC) cycles, including silicon bringup and silicon debug activities.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in fault modeling.
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
2 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in Design for Testing (DFT) scan design and verification.
Experience with Design for Testing (DFT) techniques and tools, Application-Specific Integrated Circuit (ASIC) Design for Testing synthesis, simulation, and verification flow.
Preferred qualifications:
Master's degree in Electrical Engineering.
Experience working with Automated Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
Experience in System on a chip (SoC) cycles, including silicon bringup and silicon debug activities.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in fault modeling.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
חיפה
