עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
Our Automated Driving group is looking for an VLSI Synthesis & Timing Engineer .
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
What will your job look like:
You will be responsible for the Synthesis output quality we deliver to the backend team for implementation
Develop and maintain the timing constraints and physical constraints
Debug failures and provide feedback to both RTL and BackEnd teams to rich convergence with high confidence at early stages
Define, run and debug CDC analysis
Be involved in back-annotated timing Gate-Level simulations.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
What will your job look like:
You will be responsible for the Synthesis output quality we deliver to the backend team for implementation
Develop and maintain the timing constraints and physical constraints
Debug failures and provide feedback to both RTL and BackEnd teams to rich convergence with high confidence at early stages
Define, run and debug CDC analysis
Be involved in back-annotated timing Gate-Level simulations.
Requirements:
BSc or MSc degree in Computer Engineering or Electrical Engineering.
Hands-on experience of 3 years or more in logic synthesis, Design-Compiler or Fusion-Compiler are preferable
Proven experience in defining timing constraints.
Understanding of BackEnd implementation process
Basic experience with Verilog HDL
Wide knowledge of DFT concepts.
Practical experience in Tcl scripting language
Experience with Python and/or Perl scripting languages - Advantage.
BSc or MSc degree in Computer Engineering or Electrical Engineering.
Hands-on experience of 3 years or more in logic synthesis, Design-Compiler or Fusion-Compiler are preferable
Proven experience in defining timing constraints.
Understanding of BackEnd implementation process
Basic experience with Verilog HDL
Wide knowledge of DFT concepts.
Practical experience in Tcl scripting language
Experience with Python and/or Perl scripting languages - Advantage.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
