Senior Chip Design Engineer

AWS Utility Computing (UC) provides product innovations from foundational services such as Simple Storage Service (S3) and Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

Annapurna Labs, as part of Web Services (AWS), is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.
Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.

We are looking for talented engineers to join our Chip Design team in either Tel Aviv or Haifa, working on Annapurna PCIe/IO sub-system across all product lines - Graviton, Nitro and Trainium. Our chip design team is in charge of defining the product's features and working on their architecture and development. Our team members collaborate with multiple teams from different disciplines such as product definition, pre and post silicon validation, physical design, software and others contributing to a full cycle of chip development from start to mass production. Your design will be integrated into all Annapurna's products as the IO connectivity solution for various workloads - network, storage, memory expansion and ML systems scale-up. This is an opportunity to have a large-scale impact.

Key job responsibilities
* Ownership of an SoC domain throughout the entire life cycle, from micro-architecture to tape-out sign-off
* High-level system view, including full-chip level debug and performance validation
* System-Verilog coding
* Supporting pre/post silicon Verification activities
* Ensuring that the final chip meets quality and reliability standards
* Collaborating with cross-functional teams, including: Product Definition, Verification, Emulation, Software, DFT and Physical Design
* Integration of IPs