Senior Staff Physical Engineering

At our company, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, we are a place to thrive, learn, and lead.
Your Team, Your Impact
we custom processor/ASIC solution leverages decades of expertise to deliver cutting-edge, high-performance processor chips for server, 5G/6G, automotive, and networking applications. Our team is responsible for the physical design and methodology of next-generation processors in advanced CMOS process technologies. This role provides a unique opportunity to contribute to both design execution and the development of methodologies that enable efficient and robust chip development.
What You Can Expect
Collaborate with a global team to support both physical design and methodology for complex chip projects.
Maintain, enhance, and support our Place and Route Flow using industry-standard EDA tools.
Perform synthesis, place and route, timing analysis, and timing closure for multiple intermediate and complex logic blocks.
Develop and implement timing and logic ECOs, and work with the RTL design team to address congestion and timing challenges.
Partner with the global timing team to debug and resolve block-level timing issues at the partition level.
Engage with diverse engineering challenges in a collaborative, innovative environment.