עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
We are seeking an experienced Design Engineer who thrives on complex integrations and is passionate about delivering high-quality netlists optimized for timing, power, and area. In this role, you will assume a pivotal position as the focal point for design flows and development processes, utilizing innovative technologies and collaborating closely with various teams.
The ability to independently manage tasks, represent our team optimally, and drive decisions through consensus is essential for success in this position.
In this highly visible role, you will be responsible for the top-level design development and functional design flows for both RTL and Netlist. Collaboration with design, verification, architecture, CAD, and physical design teams. You will assist team members in adopting design methodologies and contribute to their execution.
The ability to independently manage tasks, represent our team optimally, and drive decisions through consensus is essential for success in this position.
In this highly visible role, you will be responsible for the top-level design development and functional design flows for both RTL and Netlist. Collaboration with design, verification, architecture, CAD, and physical design teams. You will assist team members in adopting design methodologies and contribute to their execution.
Requirements:
Minimum Qualifications:
- 7 Years of experience in chip design.
- Experience with FE design tools and methodologies such as: Lint, Synthesis, Logic Equivalence, Clock/reset cross domain verification, FV.
- Experience in definition and implementation of low power design (UPF) - advantage.
- Ability to work collaboratively with other teams.
- Ability to develop scripts to facilitate ad-hoc design tasks.
- Quick learning of flows and methods.
Preferred Qualifications:
Relevant degree in Electrical Engineering or Computer Engineering.
- We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. We are meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that dedication. The success we are striving for is the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.
Minimum Qualifications:
- 7 Years of experience in chip design.
- Experience with FE design tools and methodologies such as: Lint, Synthesis, Logic Equivalence, Clock/reset cross domain verification, FV.
- Experience in definition and implementation of low power design (UPF) - advantage.
- Ability to work collaboratively with other teams.
- Ability to develop scripts to facilitate ad-hoc design tasks.
- Quick learning of flows and methods.
Preferred Qualifications:
Relevant degree in Electrical Engineering or Computer Engineering.
- We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. We are meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that dedication. The success we are striving for is the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
נתניה
ערב
תל אביב - יפו
3 חודשים
