עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לחפש לבד בין מאות מודעות – תנו ל-Jobify לנתח את קורות החיים שלכם ולהציג לכם רק הזדמנויות שבאמת שוות את הזמן שלכם מתוך מאגר המשרות הגדול בישראל.
השימוש חינם, ללא עלות וללא הגבלה.
Required Senior Algorithm Engineer
Communication system characterization
End-to-end communication system design
Performance analysis by simulation
Modem (PHY) algorithm design and maintenance
Code writing support including creation of test vectors and debug
Final testing support
Characterization and participation in field trials.
Communication system characterization
End-to-end communication system design
Performance analysis by simulation
Modem (PHY) algorithm design and maintenance
Code writing support including creation of test vectors and debug
Final testing support
Characterization and participation in field trials.
Requirements:
MSc/PhD in electronic engineering/signal processing
At least five years of experience in algorithms development with strong background in signal processing and wireless communication
Experience in single carrier and multicarrier modems including error correcting codes, channel equalization, AGC, clock recovery, phase recovery and tracking
Experience in designing with MATLAB/Python
Understanding of MATLAB/Python to Verilog implementation with experience in fixed-point specification and bit-accurate modelling
Laboratory work experience in algorithms debug and tuning
RTL design for FPGA, MPSoC.
Team Player, creative and independent, with strong communication and interpersonal skills
Ability to multitask and prioritize work and time including context switching
Positive attitude and professional demeanor.
MSc/PhD in electronic engineering/signal processing
At least five years of experience in algorithms development with strong background in signal processing and wireless communication
Experience in single carrier and multicarrier modems including error correcting codes, channel equalization, AGC, clock recovery, phase recovery and tracking
Experience in designing with MATLAB/Python
Understanding of MATLAB/Python to Verilog implementation with experience in fixed-point specification and bit-accurate modelling
Laboratory work experience in algorithms debug and tuning
RTL design for FPGA, MPSoC.
Team Player, creative and independent, with strong communication and interpersonal skills
Ability to multitask and prioritize work and time including context switching
Positive attitude and professional demeanor.
This position is open to all candidates.
במקום לחפש לבד בין מאות מודעות – תנו ל-Jobify לנתח את קורות החיים שלכם ולהציג לכם רק הזדמנויות שבאמת שוות את הזמן שלכם מתוך מאגר המשרות הגדול בישראל.
השימוש חינם, ללא עלות וללא הגבלה.
תל אביב - יפו
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