Senior Algorithm engineer

Requirements:
MSc/PhD in electronic engineering/signal processing At least five years of experience in algorithms development with strong background in signal processing and wireless communication Experience in single carrier and multicarrier modems including error correcting codes, channel equalization, AGC, clock recovery, phase recovery and tracking Experience in designing with MATLAB/ Python Understanding of MATLAB/ Python to Verilog implementation with experience in fixed-point specification and bit-accurate modelling Laboratory work experience in algorithms debug and tuning RTL design for FPGA, MPSoC. Team Player, creative and independent, with strong communication and interpersonal skills Ability to multitask and prioritize work and time including context switching Positive attitude and professional demeanor