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במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.

מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.

חברה בתחום הייטק / חומרה / תוכנה / סייבר

מספר מקומות

חברה בתחום הייטק / חומרה / תוכנה / סייבר

מספר מקומות
מלאה

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Own the full chip STA, analyze the timing results, verify correctness and provide budget for the different partitions.
Generate the timing constraints of complex interfaces for the STA and the P&R flow.
Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.
Help to shape the SoC clock tree, and effect the work of the different teams (Front end, DFT & BE).
Daily work involves all aspect of STA & chip design: take part in SDC generation & review, actively running & analyzing STA tools, guiding the group during chip closure process, etc'.
Taking part inflows development.
Take part in ramping up new breaking technologies.

Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
5+ years proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies with emphasis on STA (PNR, STA, physical verification).
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Excellent teammate.

This position is open to all candidates.