עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
In this role, you will work as part of a Research and Development team, building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will use design and verification expertise to verify digital designs. You will be responsible for the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or verify designs with stored value accounts and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Provide close coverage measures to identify verification holes and show progress towards tape-out.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or verify designs with stored value accounts and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Provide close coverage measures to identify verification holes and show progress towards tape-out.
Requirements:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience verifying digital logic at RTL level using SystemVerilog, Specman/E for Field Programmable Gate Arrays (FPGAs), or ASICs.
Preferred qualifications:
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.
Experience with multiple SOC projects/cycles in products.
Experience with verification techniques and the full verification life-cycle.
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience verifying digital logic at RTL level using SystemVerilog, Specman/E for Field Programmable Gate Arrays (FPGAs), or ASICs.
Preferred qualifications:
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.
Experience with multiple SOC projects/cycles in products.
Experience with verification techniques and the full verification life-cycle.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
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