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חברה בתחום הייטק / חומרה / תוכנה / סייבר

חיפה

חברה בתחום הייטק / חומרה / תוכנה / סייבר

חיפה
מלאה

Were looking for a Full Chip Layout Lead to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
IO Pad, Bump, RDL & ESD planning & implementation, co-designing with Package & Board.
Involved in chip architecture, in close collaboration with the design & architecture teams.
Exploring different floorplan structures to achieve both best area & ease of convergence.
Physical verification owner, defining Physical Verification methodologies & activities for Full Chip, Sub System & Block Level.
Working with engineers to identify and overcome roadblocks and obstacles.

Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8 years of experience in VLSI backend (RTL2GDS).
5 years of experience in Full Chip Integration & verification on complex SoCs.
Expert knowledge in floor planning, integration & signoff methodologies for hierarchical designs.
Physical Verification Expert (DRC/LVS/PERC).
Experience with IO Pad, Bump & ESD planning.
Experience in technically leading complex backend activities, preferably of complete SoC's.
Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration & Physical Signoff).

This position is open to all candidates.