עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join accelerators IP group in Beer-Sheva/Tel-Aviv , working on RiscV platform unit.
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work might involve any or all aspects of chip development: Design, micro-arch.
Work closely with Firmware and other groups around the globe.
What you will be doing:
Join accelerators IP group in Beer-Sheva/Tel-Aviv , working on RiscV platform unit.
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work might involve any or all aspects of chip development: Design, micro-arch.
Work closely with Firmware and other groups around the globe.
Requirements:
What we need to see:
University B.SC. in Electrical Engineering/Communication Engineering/Computer Engineering or equivalent experience.
2+ years experience in RTL design.
High Level of English.
Ways to stand out from the crowd:
Experienced in RTL design using VHDL/Verilog/SystemVerilog.
Experienced in CHI protocol or other cache coherence protocols.
4+ years experience in RTL design.
GPA of 85 and above.
What we need to see:
University B.SC. in Electrical Engineering/Communication Engineering/Computer Engineering or equivalent experience.
2+ years experience in RTL design.
High Level of English.
Ways to stand out from the crowd:
Experienced in RTL design using VHDL/Verilog/SystemVerilog.
Experienced in CHI protocol or other cache coherence protocols.
4+ years experience in RTL design.
GPA of 85 and above.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
רעננה
ערב
תל אביב - יפו
