עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
We are looking for a Experienced RTL Designer.
Ready for your next challenge?!
Join our family, enjoy young dynamic environment!
Work on cutting edge projects in the most attractive industry segments (automotive, perceptual computing, medical, communication, etc.)
Ready for your next challenge?!
Join our family, enjoy young dynamic environment!
Work on cutting edge projects in the most attractive industry segments (automotive, perceptual computing, medical, communication, etc.)
Requirements:
5 years hands-on System Verilog RTL coding.
Experience with tools such as VCS, Verdi, and Spyglass.
Experience debugging and working with validation using UVM.
Experience with Multiple Clock Domains, multiple power domains, low power design.
Knowledge and experience in the following is advantage:
Experience with SoC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC CPU
Experience with clock crossing interface like Gray FIFO, CDC.
Experience with Pre silicon Validation, UVM codding, Validation tools and methodology.
Experience in Full design cycle including BE design, Synthesis, Static Timing, floor planning, DFT integration.
RTL for FPGA and emulation
Experience with software and with C/C++ for reference model development. Developed drivers for ARM SoC IPs .
5 years hands-on System Verilog RTL coding.
Experience with tools such as VCS, Verdi, and Spyglass.
Experience debugging and working with validation using UVM.
Experience with Multiple Clock Domains, multiple power domains, low power design.
Knowledge and experience in the following is advantage:
Experience with SoC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC CPU
Experience with clock crossing interface like Gray FIFO, CDC.
Experience with Pre silicon Validation, UVM codding, Validation tools and methodology.
Experience in Full design cycle including BE design, Synthesis, Static Timing, floor planning, DFT integration.
RTL for FPGA and emulation
Experience with software and with C/C++ for reference model development. Developed drivers for ARM SoC IPs .
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
