Experienced Verification Engineer

Requirements:
5 years of SoC System Verilog validation experience.
Hands on experience using UVM to verify ASICs.
Advanced knowledge of System Verilog test-bench language.
Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations, formal validation.
Knowledge and experience in the following is advantage:
Experience with the full digital design verification cycle -- from spec through bring-up and prototyping and debug systems.
Experience with performance, power validation, digital design (RTL), and formal verification.
Experience with SOC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC CPU
Experience with mixed signal verification methodology for IPs such as PHYs, A2D, PLLs etc.
Experience with software and C/C++ for reference model development. Developed drivers for ARM SoC IPs.