ASIC Verification Engineer

We are looking for talented and experienced Chip Design Verification Engineers to join our Networking R&D team, developing the industry's most complex communication devices, delivering the highest throughput at lowest power and lowest latency.
Responsibilities:
Definition, architecture, and development of IP-based block-level verification environments in SystemVerilog, integrated and reused in full-chip environments.
Building reference models, verification and simulation of SOC modules according to specifications, including performance calculations.
Working in a combined design and verification team which develops the SOC silicon core units.
Working closely with multiple teams within the organization, such as Architecture, Software, and Hardware.