Verification Engineer

A premier, globally distributed Deep Tech and Semiconductor scale-up pioneering breakthrough High-Performance Computing (HPC) architectures and custom hardware accelerators for next-generation Artificial Intelligence.

Combining formidable financial backing and extensive scale with an elite, multidisciplinary engineering culture, the company offers direct ownership over core hardware programs at the absolute frontier of computing.

Located in the Central District directly adjacent to primary train transit, operating on a hybrid model with two days working from home.

Role Description-

• Serving as a Lead / Senior Silicon Verification Engineer, taking end-to-end technological ownership over the verification lifecycle for the company’s flagship HPC / AI processor core.
• Leading the 0-to-1 architecture, design, and implementation of complex, scalable verification environments from scratch using modern industry methodologies.
• Defining, architecting, and executing rigorous verification test plans to ensure zero-defect silicon quality and robust functional correctness across multi-layered SoC architectures.
• Developing modular, reusable verification components, testbenches, and checkers utilizing SystemVerilog, UVM, and advanced verification frameworks (e.g., Specman / e-language).
• Implementing advanced Constrained-Random verification methodologies, architecting comprehensive Functional Coverage models, and driving closure on Code Coverage and Assertion-based verification (SVA).
• Operating industry-standard simulation and debug engines (e.g., Synopsys VCS, Cadence Xcelium, Verdi) to isolate and root-cause complex micro-architectural bugs and corner cases.
• Collaborating intensively with Silicon Architecture, RTL Design, Firmware, and Systems Engineering squads to drive continuous quality from early architectural specification through to tape-out.

Requirements-

• B.Sc. in Electrical / Electronics Engineering or Computer Science from an accredited academic institution – Mandatory
• At least 6 years of proven professional experience in ASIC / SoC Functional Verification – Mandatory
• Proven hands-on track record of building and architecting complex verification environments from scratch – Mandatory
• Authoritative expertise in modern verification languages and methodologies: SystemVerilog and UVM – Mandatory
• Strong, practical background in Specman / e-language verification environments – Mandatory
• Deep technical understanding of SoC architecture, bus protocols, and complex digital system design – Mandatory
• Advanced, hands-on mastery of verification concepts: Constrained Random testing, Functional Coverage models, Code Coverage metrics, and Assertion-Based Verification (SVA) – Mandatory
• Extensive proficiency with industry-standard digital simulators, waveform viewers, and debug tooling – Mandatory
• Strong leadership mindset, rigorous analytical problem-solving skills, and fluent professional communication in English (written and verbal) – Mandatory