VLSI Engineer

A well-established, publicly traded global semiconductor and AI hardware company engineering cutting-edge silicon architectures, DSPs, and edge AI accelerators.

Operating internationally with hundreds of employees worldwide and a premier R&D center in Israel, the company delivers integrated hardware-software processing solutions for global chipmakers and OEMs across automotive, mobile, edge computing, and AR/VR markets.

The company pairs long-term public market stability and equity programs (RSUs) with an elite chip-design culture tackling next-generation silicon acceleration and complex PPA optimization.

Located in the Sharon District directly adjacent to the train station, operating on a hybrid model with two days working from home.

Role Description-

• Serving as VLSI / Front-End Design Team Lead, heading an engineering team of 3–4 hardware engineers within the AI VLSI department, reporting directly to the Group Manager.
• Driving full end-to-end technical ownership over the Front-End Design lifecycle for advanced silicon products—including Edge AI processors, dedicated hardware accelerators, and DSP cores.
• Guiding designs from initial architectural definitions through micro-architecture, RTL development, synthesis, verification, and silicon validation, ensuring adherence to demanding Power, Performance, Area, and Accuracy (PPAA) targets.
• Collaborating cross-functionally and globally with Architecture, Hardware Simulator, Software, and Physical Design squads to build the next-generation AI processing platforms.
• Providing hands-on technical guidance, design reviews, and mentorship to team members while optimizing team workflows and design methodologies.

Requirements-

• B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline from a leading university – Mandatory
• 4–8 years of dedicated professional hands-on experience in ASIC / SoC Front-End Design or Verification – Mandatory
• Proven, in-depth proficiency with SystemVerilog for digital design and/or verification – Mandatory
• Strong practical working knowledge and implementation experience with UVM (Universal Verification Methodology) – Mandatory
• Deep understanding of digital ASIC flow, micro-architecture specifications, and timing/power closure constraints – Mandatory
• High degree of leadership capability, technical mentorship skills, and fluent professional communication in English (written and verbal) – Mandatory