עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
An early-stage, well-funded semiconductor startup pioneering next-generation AI computing and acceleration platforms for hyperscale data centers.
Backed by tens of millions of dollars in institutional venture capital, the company brings together dozens of top-tier engineers and researchers developing high-throughput compute architectures spanning custom ASIC, CPU, GPU, and dedicated AI inference engines.
The engineering culture pairs deep silicon and hardware innovation with rapid startup execution, providing significant technical ownership from early development phases through to deployment.
The development center is located in the Sharon area, operating on a hybrid model with one day working from home (with planned expansion to an additional site in Tel Aviv adjacent to the train station).
Role Description-
- Serving as an FPGA / RTL Design Engineer (Data Path Oriented), taking hands-on ownership of high-speed data flow and subsystem architecture for next-generation AI compute platforms.
- Architecting and implementing high-throughput RTL modules focused on High-Speed Data Paths, packet/stream processing, deep buffering, arbitration schemes, and flow control mechanisms.
- Integrating custom data paths with embedded processors, on-chip and off-chip memory subsystems, and high-performance DMA engines.
- Driving full development lifecycles from microarchitecture specification and RTL coding through synthesis, timing closure, place & route, and lab bring-up.
- Collaborating cross-functionally with System Architects, Algorithm Researchers, and Low-Level Software teams to debug, profile, and optimize system-level data throughput.
Requirements-
- B.Sc. in Electrical Engineering, Computer Engineering, or an equivalent technical discipline – Mandatory
- 2+ years of hands-on experience in FPGA / RTL Design – Mandatory
- Strong coding capabilities in SystemVerilog, Verilog, or VHDL – Mandatory
- Proven hands-on experience with Data Path architecture, packet processing, streaming pipelines, or memory/DMA integration – Mandatory
- Working proficiency with major FPGA development toolchains and architectures (AMD/Xilinx or Intel/Altera) – Mandatory
- Solid laboratory bring-up, hardware debugging, and logic analysis skills – Mandatory
- Background in high-speed protocols (PCIe, Ethernet, AXI/AHB) or Data Center compute environments – Advantage
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
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