Verification Engineer

A disruptive Semiconductor startup specializing in hardware acceleration solutions for Big Data. The company’s core innovation is a custom ASIC designed to alleviate bottlenecks in data center analytics, enabling unprecedented processing speeds.

Backed by a team of industry veterans, the company is now architecting its next-generation parallel processing engine.

The company is based in a central tech hub with excellent transit accessibility and offers a high-end engineering environment at the forefront of silicon innovation.

Responsibilities-

• Verification Strategy: Defining and implementing comprehensive verification plans for the next generation of parallel processor architectures.
• Environment Construction: Designing and maintaining advanced, scalable verification environments from scratch.
• Methodology Leadership: Utilizing UVM (Universal Verification Methodology) and SystemVerilog to ensure rigorous coverage and bug discovery in complex ASIC designs.
• Advanced Protocol Validation: Verifying high-speed interfaces and complex protocols essential for data center performance.
• Cross-Functional Collaboration: Working closely with the Architecture and Design teams to influence the "Design for Verification" (DFV) strategy and resolve deep-tier architectural challenges.

Requirements-

• Academic Foundation: B.Sc. in Electrical Engineering, Electronics, or a related field – Mandatory. (M.Sc. – Significant Advantage).
• Professional Seniority: At least 10 years of experience as a Verification Engineer within the semiconductor industry – Mandatory.
• Language & Methodology: Expert-level proficiency in SystemVerilog and UVM methodology – Mandatory.
• Protocol Expertise: Proven experience with high-speed protocols and architectures, such as PCIe (Gen5+), DDR (v4+), AMBA family (AXI4+, ACE/CHI), or ARM Core architecture – Significant Advantage.
• Formal Verification: Experience with Formal Verification techniques – Advantage.
• Scripting Skills: Proficiency in scripting for automation using Python, Perl, or Shell – Advantage.
• System-Level Vision: Ability to analyze and verify complex parallel processing architectures at both the unit and system levels.