FPGA Engineer

An established, market-leading Israeli technology company engineering proprietary airspace defense and defensive cyber platforms.

The company develops an advanced counter-drone mitigation platform powered by innovative cyber-takeover technologies, delivering mission-critical airspace security for global infrastructure, defense agencies, and enterprise clients.

Operating as an autonomous business unit following an acquisition by a major global corporation, the company pairs significant financial resilience with high-impact engineering innovation.

The technical environment centers on high-speed hardware, complex RF receivers, digital signal processing (DSP), and real-time embedded systems. The office is located in Tel Aviv adjacent to the train station, operating on a hybrid model with two days working from home.

Role Description-

• Serving as the Lead FPGA / SoC Engineer, acting as the sole FPGA technical authority within the core DSP & Algorithms group, reporting directly to the Algorithms Team Lead.
• Taking end-to-end architectural and implementation ownership of high-performance FPGA and SoC platforms for advanced RF receivers.
• Architecting high-throughput data flow pipelines, high-speed interconnects, and seamless integration between Programmable Logic (PL) and Processing System (PS) / CPU.
• Implementing and optimizing digital signal processing (DSP) and communication algorithms directly onto FPGA fabric.
• Designing and integrating high-speed interfaces, high-bandwidth streaming protocols, PCIe subsystems, and DMA engines.
• Driving hands-on RTL design, functional verification, board-level hardware bring-up, and RF/system lab integration.
• Bridging the gap between Algorithm Researchers, Embedded Software engineers, and Board Designers to realize production-grade, mission-critical systems.

Requirements-

• B.Sc. in Electrical Engineering, Computer Engineering, or an equivalent technical field – Mandatory
• 6 years of hands-on experience in FPGA Design and development – Mandatory
• Deep, proven mastery in RTL design using SystemVerilog or Verilog – Mandatory
• Strong hands-on background in FPGA/SoC architectures (e.g., AMD-Xilinx Zynq / UltraScale+) and PL-PS interconnects – Mandatory
• Practical experience implementing high-speed interfaces (PCIe, DMA, AXI streaming/memory-mapped, Ethernet, SerDes) – Mandatory
• Hands-on laboratory experience with hardware bring-up, timing closure, logic analyzers, and lab test equipment – Mandatory
• Background in implementing DSP / Digital Signal Processing algorithms (filters, FFT, modulation/demodulation) on FPGA – Significant Advantage
• Practical experience working with RFSoC platforms or software-defined radio (SDR) architectures – Significant Advantage
• Prior technical leadership, mentoring, or architectural ownership experience – Advantage