System & Chip Architect

A stealth-mode, well-funded DeepTech semiconductor startup pioneering next-generation silicon architectures and AI compute platforms for hyperscale data centers.

Backed by top-tier venture capital following a substantial financing round, the company was founded by a serial semiconductor entrepreneur with a doctoral degree and a proven track record of a major technology exit.

The team is building a revolutionary AI inference accelerator chip engineered to break the critical power and memory wall bottlenecks in large-scale LLM and Generative AI workloads.

Operating with an elite team of chip architects and researchers, the firm offers a foundational role in defining future computing paradigms. The office is located in Central Israel adjacent to major transit lines, operating on a hybrid model with one day working from home.

Role Description-

• Serving as a Principal / Senior Chip & System Architect, reporting directly to the Chief Architect, leading the architectural definition of a next-generation AI inference accelerator chip from clean-sheet exploration to tape-out.
• Defining core architectural domains: Compute Fabric, Microarchitecture, Memory Hierarchy (SRAM/HBM/DDR), and high-throughput Interconnect/NoC architectures.
• Driving Design Space Exploration and PPA (Power, Performance, Area) analysis, defining optimal hardware trade-offs for modern AI/LLM workloads.
• Developing cycle-accurate / transaction-level Performance & Architecture Simulation Models in C++, SystemC, or Python prior to RTL implementation.
• Operating hands-on at the critical intersection of Algorithms ↔ Hardware ↔ Software/Compiler, translating evolving deep learning workloads into hardware-efficient computational primitives.
• Partnering closely with Front-End RTL, Design Verification (DV), Physical Design, and Compiler teams to ensure flawless silicon execution through tape-out.

Requirements-

• B.Sc. / M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related quantitative field – Mandatory
• 5 years of proven hands-on experience in System/Chip Architecture for High-Performance Compute (strong preference for AI Accelerators, GPUs, CPUs, or DSPs) – Mandatory
• Proven background from tier-1 semiconductor firms with shipped production silicon (e.g., NVIDIA, Intel, AMD, Habana/Mobileye, AWS Annapurna, Google, Broadcom, NextSilicon, or similar) – Mandatory
• Hands-on track record in Clean-Sheet Chip Architecture definition from scratch (defining novel microarchitecture and system architecture beyond standard IP block integration) – Mandatory
• Direct contribution to multiple successful tape-outs of architectures where the candidate played a key role in definition and delivery – Mandatory
• Deep theoretical and practical mastery of Computer Architecture: deep pipelines, memory hierarchies, cache coherence, NoC/interconnects, and non-von-Neumann / dataflow architectures – Mandatory
• Extensive hands-on experience developing Architecture and Performance Simulation Models (in C++, SystemC, or Python) for performance/power projection and exploration – Mandatory
• Proven ability to work cross-functionally across the algorithmic boundary, collaborating with RTL designers, verification engineers, and compiler/software teams – Mandatory