VLSI Engineer

A stealth-mode, well-funded DeepTech semiconductor startup pioneering next-generation silicon architectures and AI compute platforms for data centers.

Backed by top-tier venture capital following a substantial financing round, the company was founded by a serial semiconductor entrepreneur with a doctoral degree and a proven track record of a major technology exit.

The team is building a revolutionary AI inference accelerator chip engineered to solve the most critical power and memory wall bottlenecks in large-scale LLM and Generative AI workloads.

Operating with an elite group of chip designers and systems researchers, the firm offers a foundational role in shaping future computing platforms.

The office is located in Central Israel, operating on a hybrid model with one day working from home.

Role Description-

• Serving as a Senior ASIC / Logic Design Engineer, reporting to the Front-End Team Lead, driving the microarchitecture definition and RTL implementation of a high-performance AI inference accelerator chip for hyperscale data centers.
• Architecting and coding complex microarchitectures and high-throughput data paths in SystemVerilog / Verilog for specialized tensor compute engines, matrix multiplication units, and sophisticated memory subsystems.
• Driving subsystem integration with critical high-speed interconnects and standards, including HBM/DDR, PCIe, and ARM / RISC-V host/control subsystems.
• Collaborating closely with Compiler/Software, System Architecture, and Design Verification (DV) teams to translate evolving Generative AI workloads into silicon-efficient logic blocks.
• Executing front-end synthesis, Clock Domain Crossing (CDC) verification, Static Timing Analysis (STA), and formal checks across advanced process nodes.
• Leading rigorous PPA (Power, Performance, Area) optimization to maximize compute density and energy efficiency.

Requirements-

• B.Sc. in Electrical Engineering, Computer Engineering, or equivalent degree – Mandatory
• Deep, hands-on RTL design experience in SystemVerilog or Verilog – Mandatory
• Proven background in Microarchitecture definition from scratch, beyond implementing according to existing specifications – Mandatory
• Extensive track record designing high-speed data paths, deep pipelines, specialized compute engines, or high-throughput memory subsystems (Cache, Scratchpad, NoC) – Mandatory
• Strong architectural understanding of Compute engines and AI inference acceleration (e.g., systolic arrays, tensor/vector math, matrix multiply architectures) – Mandatory
• Practical front-end ASIC flow experience: Synthesis, CDC, Linting, and STA / Timing Closure – Mandatory
• Deep familiarity with industry-standard EDA toolchains (Synopsys, Cadence, or Siemens) – Mandatory
• Demonstrated mastery in Power, Performance, and Area (PPA) trade-offs and optimizations – Mandatory
• Familiarity with high-bandwidth memory interfaces (HBM/DDR), PCIe controllers, or RISC-V/ARM architecture – Significant Advantage