Physical Design Engineer

A stealth-mode, well-funded DeepTech semiconductor startup engineering groundbreaking AI technologies for the global chip design industry.

Founded by a prominent serial semiconductor entrepreneur with a track record of multiple tier-1 exits, the company is backed by major venture capital and employs hundreds of elite hardware and AI researchers.

The engineering culture pairs deep silicon complexity at cutting-edge nodes with fast-paced startup agility.

The company maintains two primary R&D sites located in Central Tel Aviv and the Northern Sharon region adjacent to train stations operating on a hybrid model with one day working from home.

Role Description-

• Serving as a Lead / Senior Physical Design Engineer, taking end-to-end ownership of RTL-to-GDSII implementation for complex, high-performance SoC architectures on leading-edge process nodes (5nm and below).
• Leading full-chip and block-level physical design: floorplanning, power grid design, placement, Clock Tree Synthesis (CTS), routing, and post-route optimization.
• Driving timing closure (STA) under challenging multi-corner multi-mode (MCMM) conditions, along with signal integrity (SI) and power integrity (PI) analysis.
• Executing aggressive Power, Performance, and Area (PPA) optimizations, optimizing static/dynamic power, IR-drop, and electromigration (EM).
• Developing, maintaining, and enhancing automated backend flows and design methodologies using advanced EDA toolchains.
• Partnering closely with Front-End RTL, DFT, CAD, and Foundry teams to resolve physical architecture bottlenecks and ensure smooth tape-outs.

Requirements-

• 7+ years of hands-on experience in Physical Design / Backend Implementation – Mandatory
• Deep understanding of digital design principles, physical design constraints, and timing closure methodologies – Mandatory
• Hands-on mastery of industry-standard EDA tools for Place & Route (P&R), Static Timing Analysis (STA), and Physical Verification (e.g., Synopsys Innovus / ICC2, PrimeTime, Cadence, or Siemens Calibre) – Mandatory
• Strong, hands-on scripting and automation skills in Python, Tcl, and Shell – Mandatory
• Experience with advanced process nodes (sub-7nm / 5nm and below) – Significant Advantage
• Solid background in physical verification (DRC, LVS, Antenna, ERC) and power analysis – Mandatory
• B.Sc. in Electrical Engineering, Computer Engineering, or an equivalent technical field – Mandatory