Senior Physical Design / Backend Engineer

Key Requirements & Qualifications

• Education & Experience: Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field, with 5+ years of hands-on physical design and backend implementation experience.
• Proven Tape-Out Track Record: Successful experience delivering complex, high-performance, multi-million gate SoCs through tape-out on advanced FinFET process nodes (e.g., TSMC 7nm, 5nm, 3nm or similar).
• Clock Network Expertise: Deep practical knowledge of designing, synthesizing, and debugging advanced clocking architectures. Proven experience handling skew, jitter, dynamic voltage drop (DVD), and power distribution problems specifically related to H-Trees and Clock Meshes.
• Expertise in P&R & Synthesis Tools: Expert-level mastery of industry-standard EDA physical design flows, specifically Synopsys Fusion Compiler/Innovus, Design Compiler NXT, PrimeTime, and Calibre.
• ASIC Vendor Collaboration: Direct experience working extensively with major ASIC vendors (e.g., TSMC, Samsung, Intel Foundry Services) or turnkey design services providers to resolve physical design rules and handoff requirements.
• Advanced Signoff Competence: Deep technical knowledge of timing closure patterns, multi-voltage/power-gated designs (UPF/CPF), and high-frequency routing techniques.
• Startup Agility: Exceptional capability to thrive in a fast-paced, high-ambiguity startup environment. A pragmatic engineer who knows how to balance meticulous physical design optimization with aggressive tape-out schedules.
• Automation & Scripting: Strong proficiency in Tcl, Python, or Perl to build, customize, and maintain physical design infrastructure and tool flows.