Hardware Design Engineer

Meet Arago and the Aragonians

Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors.

Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.

Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements.

Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European Deeptech venture firms and exited founders.

What you’ll do

Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface Arago’s custom tensor unit for advanced AI/ML applications.

Responsibilities

• Design, implement, and verify RTL blocks for memory, control, and compute subsystems within Arago’s custom Multiphysics computation unit.
• Collaborate with Arago’s system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.
• Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.
• Support synthesis, timing analysis, and backend integration, working closely with Arago’s physical design and CAD engineers.
• Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of Arago’s compute platform.

Required Skills and Experience

• Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, Datapath, memory subsystems, and specialized processing units.
• Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration.
• Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus).
• Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT.
• Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support.
• Language: English at a proficient level. French is a plus.

Pay and benefits

• Competitive cash compensation, with package based on location and experience
• Flexible Work setting, no strict office requirement
• Spacious office in Central Area with a Gym
• Option for a relocation & bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.
• Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers).
• Healthcare coverage (including family-friendly options), pension contributions, Keren Hishtalmut
• Professional development support and 20 days of PTO, in addition to public holidays.
• A high-paced, multicultural (with 9 nationalities), and engineering-led environment.